ASIC Design of Reversible Multiplier Circuit- A Review
Volume: 5 - Issue: 05 - Date: 01-05-2016
Approved ISSN: 2278-1412
Published Id: IJAECESTU271 | Page No.: 983-986
Author: Anand dayal
Co- Author: Himanshu shekhar
Abstract:-Reversible logic is extremely a lot of in demand for the longer term computing
technologies as they're known to provide low power dissipation having its applications in Low
Power, Quantum Computing, nanotechnology, and Optical Computing. The planning of reversible
multiplier factor circuit relies on invertible primitives and composition rules that preserve
invertibility. during this paper we've got given and implemented reversible Wallace signed
multiplier factor circuit in ASIC through changed Baugh-Wooley approach using normal
reversible logic gates/cells, supported complementary pass transistor logic and are valid with
simulations, schematic check, and a style rule check. The planned reversible multiplier factor is
faster and has lower hardware complexness compared to the present counterparts. it's proved that
the planned multiplier factor is best and optimized, compared to Its existing counterparts with
reference to the amount of gates, constant inputs, garbage outputs and hardware complexness.
Key Words:-Reversible logic gates, Reversible logic circuits, Quantum Computing Systems, Wallance Signed multiplier, Baugh-Wooley approach
Area:-Engineering
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