Reversible logic is extremely a lot of in demand for the longer term computing technologies as they're known to provide low power dissipation having its applications in Low Power, Quantum Computing, nanotechnology, and Optical Computing. The planning of reversible multiplier factor circuit relies on invertible primitives and composition rules that preserve invertibility. during this paper we've got given and implemented reversible Wallace signed multiplier factor circuit in ASIC through changed Baugh-Wooley approach using normal reversible logic gates/cells, supported complementary pass transistor logic and are valid with simulations, schematic check, and a style rule check. The planned reversible multiplier factor is faster and has lower hardware complexness compared to the present counterparts. it's proved that the planned multiplier factor is best and optimized, compared to Its existing counterparts with reference to the amount of gates, constant inputs, garbage outputs and hardware complexness.