The need of low area and high speed Multiplier is increasing as the need of high speed processors are needed. Vedic arithmetic is that the traditional system of arithmetic which has a novel technique of calculations supported sixteen Sutras that are discovered by Sri Bharti Krishna Tirthaji. Any processor’s performance depends on 3 vital factors specifically speed, space and power. a higher trade-off between these factors makes the processor, a good one. Multipliers are the usually used architectures within the processor. If the performance of those multipliers is improved then powerful processors is created in future. During this work, the planned number style supported the sutra- ‘Urdhva Tiryakbhyam’ of Vedic arithmetic is analyzed and also the performance results of the number are compared with standard multipliers. The multipliers used in Square and cube architecture have to be more efficient in area and also in speed. In this proposed work a multiplier is implemented based on Nikhilam sutra with binary excess unit. The ripple carry adder in the multiplier architecture increases the speed of addition of partial products. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.