- Adders are important building blocks in many digital systems and the performance of these systems depends mainly on the speed of addition, power consumption and area occupied by the adder circuit. Portable and battery operated devices require very low power for their efficient operation. In this work a carry save adder is designed using pipelined architecture to improve the speed and implemented with efficient charge recovery logic (ECRL) for reducing the power dissipation. The simulations carried out using Mentor Graphics tool at 130 nm technology node indicate an improvement of 99.4% in speed with pipelining for the static CMOS 4-bit carry save adder. With ECRL logic the power dissipation is found to be lowered by 46.3% as compared to static CMOS pipelined adder.