Designing of power-efficient and high speed digital logic systems is very crucial task. Numbers of adders are designed and supply tradeoffs between power, delay and space. The carry propagation delay and space of carry select adder is reduced by splitting carry select adder into equal bit groups. In [1] to extend speed, whereas doing the multiplication or addition operations, has perpetually been a basic demand of planning of advanced system and application. Carry select Adder (CSLA) is one of the quickest adders employed in several data-processing processors to perform quick arithmetic functions. From the structure of the CSLA, it's clear that there's scope for reducing the area and power consumption in the CSLA. In this paper review/survey of previous work related to Fast FIR filter compressor and carry select adder.