This paper presents a new algorithmic rule to construct an XOR-Free design of a power efficient Convolutional Encoder. Optimisation of XOR operators is the main concern while implementing polynomials over GF that consumes a significant quantity of dynamic power. The projected approach completely removes the XOR-processing operation of a chosen nonsystematic, reduces the logical operators and feed-forward generator polynomial, thereby the encoding cost. Implementation of the projected design uses read-only storage (ROM) with preprocessed addressing operations to reduce read-only memory size by about five hundredth. The outcomes of the new architecture reduce the dynamic power up to 21.4% and value up to fifteen with lesser design complexness as compared to standard technique. Due to the excellent error control performance in many communication systems Convolution encoder and Viterbi decoder are widely used. In coding techniques the number of symbols in the source encoded message is increased in a controlled manner in order to facilitate 2 basic demand at the receiver one is Error detection and other is Error correction. Coding could be a technique where redundancy is added to original bit sequence to extend the reliability of the communication. This paper presents a review on implementation of power efficient architecture of Convolution Encoder