The importance of energy-efficient processor design is recognized in designing of Ultra low power processor design. CSKA structure presented here is able to achieve a very high speed in comparison to normal carry skip adder. The most prominent application of proposed structure is in the field of ALU design for microprocessors. Main focus of this work is on the synthesis and simulation of high speed adders. These high speed adders are designed using different architecture as the basic building blocks for complete structure on Vivado using VHDL language and the results are further compared with several other adder structures. These high speed adder structures not only minimize the total energy consumption of the system but also reduce the time taken by each arithmetic operation i.e. increase the system operating speed. A CSKA structure is proposed in [1], the presented structure is both Power and area efficient. Total path delay of the CSKA is smaller as compare to that of RCA and CLA. Area requirement of CI_CSKA is high as compare to the RCA and CLA, while power delay product of this CI_CSKA structure presented in this paper is less among the three