The need for low power integrated circuits is well known because of their extensive use in the electronic portable equipments. On chip SRAMs (Static Random Access Memory) determine the power dissipation of SoCs (System on Chips) in addition to its speed of operation. Hence it is very important to have energy efficient SRAMs. This Thesis proposes energy efficient SRAM cells (7T) based on adiabatic principles and design modifications. Bulk of the energy in SRAMs is wasted during charging of the bit lines and discharging it to the ground during read and writes operations. It is proposed to use adiabatic approach to collect this energy and recycle it. Based on this thought process a separate and simple adiabatic driver circuit has been designed and used for bit line charging. It is shown that in 6T SRAM, a total energy of the order of 50% over a given period and around 80% during write cycle can be saved by the help of this driver. With this adiabatic driver circuit working in conjunction with conventional 7T SRAM cell other performance characteristics like read stability, write ability, read and write delay etc have been found by simulation in addition to energy saving under varied conditions of memory operations. The effect of device parameters of the driver on total energy of the SRAM cell has been investigated. Further studies covered proposed SRAM cell arrays. With a view to increase energy saving further, the possibility of having adiabatic SRAM with single bit line for reading and writing is examined. This architecture improves the total energy saving further (90%). Feat SRAM is designed to get better speed of operation along with energy saving.