Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced DataIndependent Read Port Leakage for Array Augmentation in 32-nm CMOS
Volume: 10 - Issue: 08 - Date: 01-08-2021
Approved ISSN: 2278-1412
Published Id: IJAECESTU361 | Page No.: 110-116
Author: Alisha Jabeen
Co- Author: Ashish Raghuwanshi
Abstract:-In a ultralow voltage operation of Digital Circuits will improve the
performance in all application with high constraints, energy efficiency and low power
consumptions. In this area memory system will take major role to storing and retrieving
data with using SRAM memory cells. This SRAM will have lot of complexity in Write
and Read operations due to more number of Transistors, thus it will choose column and
row selection method. In this proposed work will hybrid two single ended (SE)
differential SRAM for write and read operation to reduced the hardware complexity and
power consumption, for write operation 6T SRAM will used and for read operation 4T
SRAM will used, it will take totally 10T SRAM. This technique is adopted using
differential VDD technique to improved write ability of the design. Further the proposed
architecture will designed up to 8-Bit 10T SRAM cell to test and proved the efficiency.
Finally this work will developed in Tanner EDA using 45nm CMOS Technology with 1V
supply voltage and proved the comparisons with existing 65nm CMOS Technology in
terms of area, delay and power.
Key Words:-SRAM,SE10T SRAM, 45nm, Power optimization, Area optimization
Area:-Engineering
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