Survey paper on Floating Point Multiplier Architectures on FPGA
Volume: 7 - Issue: 02 - Date: 01-02-2018
Approved ISSN: 2278-1412
Published Id: IJAECESTU348 | Page No.: 101-105
Author: Osho Patil
Co- Author: Paresh Rawat
Abstract:-This paper presents FPGAs used to be fixed-point.
Floating-point operations are useful for computations
involving large dynamic range, but they require
significantly more resources than integer operations. Multipliers play an important role in today’s digital
signal processing and various other applications.
With advances in technology, many researchers have
tried and are trying to design multipliers which offer
either of the following design targets – high speed,
low power consumption, regularity of layout and
hence less area or even combination of them in one
Multiplier thus making them suitable for various high
speed, low power and compact VLSI implementation.
Field Programmable Gate Arrays (FPGAs) are
semiconductor devices that are based around a matrix
of configurable logic blocks (CLBs) connected via
programmable interconnects. FPGAs can be
reprogrammed to desired application or functionality
requirements after manufacturing. This feature
distinguishes FPGAs from Application Specific
Integrated Circuits (ASICs), which are custom
manufactured for specific design tasks.
Key Words:-Floating Point Arithmetic, Multipliers, Digital Arithmetic, FPGA
Area:-Engineering
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