Result Analysis of Low power and area efficient Reverse Converter Design via Parallel-Prefix Adders
Volume: 6 - Issue: 05 - Date: 01-05-2017
Approved ISSN: 2278-1412
Published Id: IJAECESTU303 | Page No.: 514-518
Author: Mukesh Kumar Pandey
Co- Author: Suresh Gawande
Abstract:-– The implementation of residue number system reverse converters based on well-known
regular and modular parallel prefix adders is analyzed. The VLSI implementation results show a
significant delay reduction and area × time2 improvements, all this at the cost of higher power
consumption, which is the main reason preventing the use of parallel-prefix adders to achieve
high-speed reverse converters in nowadays systems. Hence, to solve the high power consumption
problem, novel specific hybrid parallel-prefix-based adder components those provide better
tradeoff between delay and power consumption. The power, area and delay of the proposed system
are analysis using Xilinx 14.2
Key Words:-parallel-prefix adder, residue number system (RNS), reverse converter.
Area:-Engineering
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