A Novel Logic Style Used For Leakage Power Reduction inMOS Integrated Circuit
Volume: 5 - Issue: 04 - Date: 01-04-2016
Approved ISSN: 2278-1412
Published Id: IJAECESTU270 | Page No.: 987-991
Author: Abhijeet Washishtha
Co- Author: Tina Raikwar
Abstract:-– Full adders are necessary parts in applications corresponding to digital
signal processors (DSP) architectures and microprocessors. Additionally to its main task,
that is adding 2 numbers, it participates in several different helpful operations appreciate
subtraction, multiplication, division, address calculation, etc. In most of those systems the
adder lies in the critical path that determines the general speed of the system. Therefore
enhancing the performance of the 1-bit full adder cell (the building block of the adder)
could be a significant goal. Demands for the low power VLSI approaching the expansion
of insistent design process to control use severely. To accomplish the rising demand, we
advise a new low power adder by give up the MOS transistor calculate that reduce the
grave threshold defeat so anew enhanced 14T CMOS l-bit full adder cell is specified in
this paper. Results show five hundredth improvement in threshold loss drawback, 45%
improvement in speed and considerable power consumption over the given adder and
other different types of adders with comparable presentation.
Key Words:-Arithmetic circuit, full adder, multiplier, low power, very Large-scale integration (VLSI).
Area:-Engineering
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