Design Area-Efficient and high speed 32bit CSLA
Volume: 4 - Issue: 08 - Date: 01-08-2015
Approved ISSN: 2278-1412
Published Id: IJAECESTU248 | Page No.: 555-559
Author: Malti Aryayan
Co- Author: Jaikaran Singh Chauhan
Abstract:-Modern applications demand extremely less area budgets and enhanced speed in
computer architectures for battery-operated devices like Laptop and others. In this thesis, the
main focus is on the area and provides high speed to the processors. Less area and high speed
circuits are becoming more desirable due to growing portable device markets and they are also
becoming more applicable today in processors. The main focus in this work is to improve the
speed of the 32-bit processor and in this case the carry select adder is the better choice. The
second concern in the design of this carry select adder is the reduction of area that is achieved by
implementing the internal structure of the ripple carry adder in the branching architecture. The
approach used here is to implement these pipelines in a manner that only one pipeline will be
activated through which the carry is propagating. Furthermore, RTL level optimizations have also
been done to ensure less area during intermediate computations. In this thesis, the entire adder
architecture has been implemented using Verilog and simulated using ISE tool suite. It provides a
good improvement in speed as well as reduces the area requirement to a greater extent.
Key Words:-CSLA,RCA,BCD,32 Bit CSLA
Area:-Engineering
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