Speed Enhancement In DDR3 SDRAM Using FIFO Synchronization Technique
Volume: 3 - Issue: 08 - Date: 01-08-2014
Approved ISSN: 2278-1412
Published Id: IJAECESTU231 | Page No.: 351-354
Author: VinusTyagi
Co- Author: Rahul Shrivastava,Rita Jain
Abstract:-The demand for high speed and small size memories has been increasing by the day. All
device size is decreasing day-by-day in electronics industry for the best handing and carrying.
Hence, these memory devices are rapidly developing to give high density and high memory
bandwidths. However, with the increase in technology, complexity of instructions to control the
memory devices also increases. This paper presents the technique and architecture of the DDR3
Controller which can be used to enhance the speed and discuss advantages of DDR3.
Key Words:-Double Data Rate(DDR), First-In First-Out (FIFO), Field Programmable Gate Array(FPGA), Finite State Machine(FSM), Input-Output(I/O), Integrated Software Environment(ISE), Static Dynamic Random Access Memory(SDRAM), Look-Up-Table(LUT), Random Access Memory(RAM).
Area:-Engineering
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